Join one of the most technically advanced FPGA teams in Australia, designing cutting-edge systems where you'll be working on high-performance, timing-critical designs. This is a role for engineers who enjoy pushing FPGAs to their limits—where MHz matter, timing margins are tight, and LUTs must be used with precision. The role is based in Sydney CBD and offers a hybrid work arrangement. What You’ll Work On: Architect and implement FPGA designs running at higher clock frequencies, with strict timing and deterministic performance requirements. Optimise datapaths for throughput and latency, balancing pipeline depth and logic resource usage (LUTs, FFs, DSPs). Integrate FPGA modules with embedded systems, processors, and high-speed interfaces (e.g., PCIe, Ethernet, HBM, DDR4, AXI) Drive the complete design cycle—from RTL through synthesis, timing closure, and lab validation on real hardware. Collaborate with a multidisciplinary team of hardware, software, and systems engineers on highly integrated products. Your Skillset: Excellent knowledge of VHDL / Verilog for high-speed designs Understanding of synchronous design techniques and how to keep designs stable when things get complex Familiarity with Vivado timing analysis, debugging, and scripting (Tcl/Python) for build/test automation. Knowledge of Ethernet, and OSI layer model (desirable) The Other Stuff: The position is based in Sydney CBD. Full working rights in Australia - permanent residency, Australian citizenship, or a valid working visa. Onsite or video interviews available. Offering excellent salary package and bonuses Please feel free to get in touch with any questions. Luke Johnson, Recruitment Consultant P: 0466 210 441 E: luke@codematix.com.au You can find out more about Codematix by visiting www.codematix.com.au
